The integrated circuit (IC) manufacturing technology have been moving forward as the metal-oxide-semiconductor field-effect transistors (MOSFET's) become smaller and smaller to improve the performances such as increased switching speed, lowered power consumption and higher level of integration. In view of device isolation, shallow trench isolation (STI) technology has advantages over the conventional local oxidation of silicon (LOCOS) technology. For example, STI technology shrinks the surface area needed to isolate transistors while offering superior latch-up immunity, smaller channel-width encroachment and better planarity.
However, STI technology encounters many challenges. For example, chemical-mechanical polishing (CMP) with different pattern densities may result in over-polishing to cause dishing in the trench in the low pattern density region. As a result, open circuits occur due to collapse or breaks in the metal interconnects.
To overcome the problems due to dishing with STI technology, U.S. Pat. No. 6,372,605 provides a method using an additional oxide-reduction etching step performed prior to chemical-mechanical processing so as to reduce the polishing time to prevent dishing for shallow trench isolation processing.
In the present invention, provided are shallow trench isolation structures in a semiconductor device and a method for manufacturing the shallow trench isolation structures by depositing a high-k material layer in a trench with a larger surface area to improve surface planarity of the semiconductor device.